[SOLVED] concurrent system verilog assertions

[pramodh]

Hi,
I am new into sva and have been trying out some examples on concurrent sva's.The code I have been trying out is for simple and gate.This code is working fine for immediate assertions but for concurrent assertions, it is giving errors. I have pasted both the code and error. Help me out. Thanks

module an();
reg clk;

class anbn;
rand logic a;
rand logic b;
logic c;
endclass

anbn a1;
initial
begin
a1=new();
end

always
#5 clk=~clk;

always @(posedge clk)
begin

for(int i=0;i<10;i++)
begin
a1.randomize();
a1.c=a1.a && a1.b;
$display("a=%b,b=%b",a1.a,a1.b);
$display("c=%b\n \n",a1.c);
end

#1000 $finish;
end

aa:assert property(@(posedge clk) $rose(a1.a && a1.b) |-> $rose(a1.c));
endmodule

The output is
Error-[ETTNATE] Expressions of this type not allowed in temporal expressions
Expressions of real, string and event types, as well as dynamic
SystemVerilog types, are not allowed in temporal expressions
Expression: a1.a
"practise.sv", 36: aa: assert property(@(posedge clk) ($rose((a1.a &&
a1.b)) |-> $rose(a1.c)));

Error-[ETTNATE] Expressions of this type not allowed in temporal expressions
Expressions of real, string and event types, as well as dynamic
SystemVerilog types, are not allowed in temporal expressions
Expression: a1.b
"practise.sv", 36: aa: assert property(@(posedge clk) ($rose((a1.a &&
a1.b)) |-> $rose(a1.c)));

Error-[ETTNATE] Expressions of this type not allowed in temporal expressions
Expressions of real, string and event types, as well as dynamic
SystemVerilog types, are not allowed in temporal expressions
Expression: a1.c
"practise.sv", 36: aa: assert property(@(posedge clk) ($rose((a1.a &&
a1.b)) |-> $rose(a1.c)));

3 errors

 

[ljxpjpjljx]

random variable is not allowed, please try to use other types!

 

[pramodh]

It worked with random variables. It is not working when we call variables through object like a1.a, a1.b, a1.c..Not getting the reason..

 

[pramodh]

got the solution from
**broken link removed**