Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Concepts of Turn-on Breakdown

Status
Not open for further replies.

firry

Junior Member level 3
Joined
Dec 3, 2005
Messages
28
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,473
Hi,
I have a MOS model that will occur breakdown when Vds>4V,which is called turn-on breakdown. If the FET in cut off region and Vds>4V, will it occur breakdown? Is the term turn-on breakdown means the FET will breakdown when it is work(Vgs>Vth)?
Can anyone give me a document or describing the concepts of Turn-on Breakdown?

Regards,
Firry.
 

i don't understand your question
but what i know is
there us condition called velocity saturation
it happens when applying voltage greater than the voltage which is caused saturation in velocity of electrons
in cut off; ther is no current pass because there is no channel created
 

firry said:
Hi,
I have a MOS model that will occur breakdown when Vds>4V,which is called turn-on breakdown. If the FET in cut off region and Vds>4V, will it occur breakdown? Is the term turn-on breakdown means the FET will breakdown when it is work(Vgs>Vth)?
Can anyone give me a document or describing the concepts of Turn-on Breakdown?

Regards,
Firry.

Here
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top