computing logical effort

[asicengineer1]

Hi,
i've a basic question on logical effort. if we compute the ratio of sum of capacitances of the gate to an ideal gate (inverter), we get the logical effort.

if 2-input NAND gate has 2 NMOS in series, 2 PMOS in parallel, then, shouldn't the total capacitance of gate be 5 ? and the LE should be equal to 5/3, right ? but, i saw its given as 4/3. can anyone explain where i'm going wrong ?

thanks.

 

[vak]

Logical Effort by Sutherland and Sproull may be useful

 

[cl_mos]

1) p-mos has about have the drive strength that an n-mos does due to hole vs electron mobility. To get same fall/rise edge rate the p-mos has to be 2x the nmos.
2) A 2 stack series device is required to be 2x the size of just a single transistor.
3) A parallel device might have only one of the legs turn on so all the legs have to be sized as if only one might turn on so this means 1x.

NAND : 2 NMOS in series 2x due to series connection and 1x due to NMOS = 2x
PMOS : 2 PMOS parallel 1x due to parallel device and 2x due to PMOS = 2x

One input is connected to 1 NMOS (2) and 1 PMOS (2). 2+2 =4 and as you said the inverter is 3 so the logical effort for each input of the NAND is 4/3.

Hope this helps. Any as vak says the Logical effort is a great book on this.