Component Instantiation Or Procedure better in VHDL

[nandakishore.mehrwade]

In my project i have two decoders which runs iteratively, each has same three modules in it. I want performance in terms of speed and hardware. Priority is for speed followed by hardware.
Among component instantiation and procedure, which will give me better performance.
Anyone who knows about these please guide me, and let me know what are advantages and disadvantages of these two. Thanks in advance.

 

[TrickyDicky]

Its an invalid question, because either can be better or worse depending on the logic it creates. Procedures on their own cannot contain wait statements inside them for synthesis, so registers have to be created in the calling process.

But it doesnt matter how you do it, its the logic thats created that is the important bit.