Complex muliplication and addition in VHDL radix 2 FFT project

[sougata_vlsi13]

Sir,currently I am working on radix 2 FFT project.I have written the code for radix 2 DIT FFT butterfly structure.i have written the code in 4 modules.but in case of calculating the formula like
S(0)=x(0)+W(0)*x(4), like x(0)=0.5;w(0)=0.7+j0.5 and x(4)=0.5


it needed complex multiplication and addition,i am not getting how to write it in VHDL.although i have taken function add,sub and mult and also describe it in a separate package but while running the test bench with thre required input it is showing some fatal error like your product value is out of range.


prod.r:=(p1.r * p2.r) - (p1.i * p2.i);---error
prod.i:=(p1.r * p2.i) + (p1.i * p2.r);---error

please help me in this regard

 

[TrickyDicky]

Post some of your code, and copy/paste the errors.

 

[sougata_vlsi13]

Post some of your code, and copy/paste the errors.

here is the code
1.FFT_main module
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fft_pkg.all;

entity fft_eightpt is
port(x:in comp_array ; --input in time domain
zut comp_array); --output in frequency domain
end fft_eightpt;

architecture behav of fft_eightpt is
component butterfly is
port(x1,x2:in complex; --input
w: in complex; --twiddle factor
g1,g2ut complex); --output but acting as input to 2nd and 3rd stage
end component;

signal g1,g2 : comp_array := (others => (0.0,0.0));
constant w:comp_array2:=((1.0,0.0),(0.707,-0.707),(0.0,-1.0),(-0.707,-0.707));
begin

--1st stage of butterfly mapping
buf11:butterfly port map(x(0),x(4),w(0),g1(0),g1(1));
buf12:butterfly port map(x(2),x(6),w(0),g1(2),g1(3));
buf13:butterfly port map(x(1),x(5),w(0),g1(4),g1(5));
buf14:butterfly port map(x(3),x(7),w(0),g1(6),g1(7));

--2nd stage of butterfly mapping
buf21:butterfly port map(g1(0),g1(2),w(0),g2(0),g2(2));
buf22:butterfly port map(g1(1),g1(3),w(2),g2(1),g2(3));
buf23:butterfly port map(g1(4),g1(6),w(0),g2(4),g2(6));
buf24:butterfly port map(g1(5),g1(7),w(2),g2(5),g2(7));

--3rd stage of butterfly mapping
buf31:butterfly port map(g2(0),g2(4),w(0),z(0),z(4));
buf32:butterfly port map(g2(1),g2(5),w(1),z(1),z(5));
buf33:butterfly port map(g2(2),g2(6),w(2),z(2),z(6));
buf34:butterfly port map(g2(3),g2(7),w(3),z(3),z(7));

end behav;

2.FFT_pack
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.ALL;

package fft_pkg is

type complex is
record
r : real;
i : real;
end record;

type comp_array is array (0 to 7) of complex;
type comp_array2 is array (0 to 3) of complex;

function add (n1,n2 : complex) return complex;
function sub (n1,n2 : complex) return complex;
function mult (n1,n2 : complex) return complex;

end fft_pkg;

package body fft_pkg is

--addition of complex numbers
function add (n1,n2 : complex) return complex is

variable sum : complex;

begin
sum.r:=n1.r + n2.r;
sum.i:=n1.i + n2.i;
return sum;
end add;

--subtraction of complex numbers.
function sub (n1,n2 : complex) return complex is

variable diff : complex;

begin
diff.r:=n1.r - n2.r;
diff.i:=n1.i - n2.i;
return diff;
end sub;

--multiplication of complex numbers.
function mult (n1,n2 : complex) return complex is

variable prod : complex;

begin
prod.r:=(n1.r * n2.r) - (n1.i * n2.i);
prod.i:=(n1.r * n2.i) + (n1.i * n2.r);
return prod;
end mult;

end fft_pkg;


Error:showing fatal error while running the test bench and showing product value is out of range.I have also declared one separate module for butterfly component.

 

[TrickyDicky]

what is the actual error? Please copy/paste it.

 

[sougata_vlsi13]

what is the actual error? Please copy/paste it.

Sir I am pasting here the complete code...please help me in this regard

1.1st module:-

--FFT_main


library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.fft_pkg.all;

entity fft_eightpt is
port(x:in comp_array ; --input in time domain
zut comp_array); --output in frequency domain
end fft_eightpt;

architecture behav of fft_eightpt is
component butterfly is
port(x1,x2:in complex; --input
w: in complex; --twiddle factor
g1,g2ut complex); --output but acting as input to 2nd and 3rd stage
end component;

signal g1,g2 : comp_array := (others => (0.0,0.0));
constant w:comp_array2:=((1.0,0.0),(0.707,-0.707),(0.0,-1.0),(-0.707,-0.707));
begin

--1st stage of butterfly mapping
buf11:butterfly port map(x(0),x(4),w(0),g1(0),g1(1));
buf12:butterfly port map(x(2),x(6),w(0),g1(2),g1(3));
buf13:butterfly port map(x(1),x(5),w(0),g1(4),g1(5));
buf14:butterfly port map(x(3),x(7),w(0),g1(6),g1(7));

--2nd stage of butterfly mapping
buf21:butterfly port map(g1(0),g1(2),w(0),g2(0),g2(2));
buf22:butterfly port map(g1(1),g1(3),w(2),g2(1),g2(3));
buf23:butterfly port map(g1(4),g1(6),w(0),g2(4),g2(6));
buf24:butterfly port map(g1(5),g1(7),w(2),g2(5),g2(7));

--3rd stage of butterfly mapping
buf31:butterfly port map(g2(0),g2(4),w(0),z(0),z(4));
buf32:butterfly port map(g2(1),g2(5),w(1),z(1),z(5));
buf33:butterfly port map(g2(2),g2(6),w(2),z(2),z(6));
buf34:butterfly port map(g2(3),g2(7),w(3),z(3),z(7));

end behav;


2nd module:-

--FFT_package


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.ALL;

package fft_pkg is

type complex is
record
r : real;
i : real;
end record;

type comp_array is array (0 to 7) of complex;
type comp_array2 is array (0 to 3) of complex;

function add (n1,n2 : complex) return complex;
function sub (n1,n2 : complex) return complex;
function mult (n1,n2 : complex) return complex;

end fft_pkg;

package body fft_pkg is

--addition of complex numbers
function add (n1,n2 : complex) return complex is

variable sum : complex;

begin
sum.r:=n1.r + n2.r;
sum.i:=n1.i + n2.i;
return sum;
end add;

--subtraction of complex numbers.
function sub (n1,n2 : complex) return complex is

variable diff : complex;

begin
diff.r:=n1.r - n2.r;
diff.i:=n1.i - n2.i;
return diff;
end sub;

--multiplication of complex numbers.
function mult (n1,n2 : complex) return complex is

variable prod : complex;

begin
prod.r:=(n1.r * n2.r) - (n1.i * n2.i);
prod.i:=(n1.r * n2.i) + (n1.i * n2.r);
return prod;
end mult;

end fft_pkg;

3rdmodule:-

--FFT_butterfly_component

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fft_pkg.all;

entity butterfly is
port(x1,x2:in complex;
w:in complex;
g1,g2ut complex);
end butterfly;

architecture behav of butterfly is
begin
g1<= add(x1,mult(x2,w));
g2<= sub(x1,mult(x2,w));
end behav;


4th module:-

--FFT_testbench

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fft_pkg.all;


entity test_bench is
end test_bench;

architecture behav of test_bench is
signal x,z:comp_array;
begin
DUT:entity work.fft_eightpt port map
(x=> x,
z=>z);
process
begin
x(0) <= (0.5,0.0);
x(1) <= (0.5,0.0);
x(2) <= (0.5,0.0);
x(3) <= (0.5,0.0);
x(4) <= (0.0,0.0);
x(5) <= (0.0,0.0);
x(6) <= (0.0,0.0);
x(7) <= (0.0,0.0);
wait;
end process;
end behav;


This is the complete code.there is no compilation error but while simulation the test bench(4th module) in the code it is saying product value is out of range.sir please help me in this regard.

 

[TrickyDicky]

Please copy and paste the error - not the code.
But I suspect its your input values causing the problem.

PS. WHat are your goals? you cannot synthesise this code for hardware.

 

[sougata_vlsi13]

Please copy and paste the error - not the code.
But I suspect its your input values causing the problem.

PS. WHat are your goals? you cannot synthesise this code for hardware.

Yes of course i cannot synthesize the code because i am taking floating point values but actually i want to know about the error...means why it is coming although i have not specified any range.i just want to implement the butterfly structure.Sir please once if possible run the test bench once.


vsim -gui work.test_bench
# vsim -gui work.test_bench
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.math_real(body)
# Loading work.fft_pkg(body)
# Loading work.test_bench(behav)
# Loading work.fft_eightpt(behav)
# Loading work.butterfly(behav)
add wave -r /*
run
# ** Fatal: (vsim-3421) Value 1.414e+308 for prod is out of range -1e+308 to 1e+308.
# Time: 0 ps Iteration: 0 Process: /test_bench/dut/buf34/line__16 File: C:/Windows/System32/FFT_butfcomp.vhd
# Fatal error in Subprogram mult at C:/Windows/System32/FFT_pack.vhd line 53
#
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.
run
# Cannot continue because of fatal error.

 

[TrickyDicky]

Its because x, at time 0, is not given a specific default value, so everything defaults to the minimum value of real, -1e+308. This will quickly overflow the range of real with your code.

SO I suggest giving X a default value.

 

[sougata_vlsi13]

Its because x, at time 0, is not given a specific default value, so everything defaults to the minimum value of real, -1e+308. This will quickly overflow the range of real with your code.

SO I suggest giving X a default value.

sir,where to give the default value becoz i have declared x as a comp_array

 

[TrickyDicky]

when you declare it:

signal x : comp_array := (others => (0.0, 0.0) );

 

[sougata_vlsi13]

so do i need to remove it...and give some default value there

 

[TrickyDicky]

remove what? all you need to do is give X a default value when you declare it. You process is pretty redundant if you do this, because you're just overriding the default value.

 

[sougata_vlsi13]

remove what? all you need to do is give X a default value when you declare it. You process is pretty redundant if you do this, because you're just overriding the default value.

ok thank you sir

 

[sougata_vlsi13]

sir still now some compilation error is coming...i am not getting how to give the default value to x.the line which u have written
signal x : comp_array := (others => (0.0, 0.0) ); it is not for x it is for signal g1 and g2.when i am assigning any default value to x in the entity part it is not taking that value rather showing the error not compatible with work.fft_pkg........so sir what to do....please help me

- - - Updated - - -

sir still now some compilation error is coming...i am not getting how to give the default value to x.the line which u have written
signal x : comp_array := (others => (0.0, 0.0) ); it is not for x it is for signal g1 and g2.when i am assigning any default value to x in the entity part it is not taking that value rather showing the error not compatible with work.fft_pkg........so sir what to do....please help me

 

[sougata_vlsi13]

please anyone help me with the error what is coming in the product part of FFT package