Compensation issue in buck DC/DC design

[tonywai]

Hi All
I am studying buck DC/DC now.
For voltage control pwm, some papers introduce the typeII and typeIII compensation. But when I study some datasheet like TI's TPS62300,TPS65023...
It looks there is no external compensation RC with voltage control mode.

Can anybody give me some idea on how to fulfill this compensation? Internal compensation RC will cost large area, and It also mention that feedforward compensation. Does it mean slope of pwm ramp changes with input voltage?

Thanks!

Tony

 

[harrytrinh]

Re: DCDC design issue

If you didn't see the external RC then it should be internal. For DC-DC we need to have compensation to make output stable. About feedforward compensation, that is adding one zero and one pole by adding a feedforward cap from out put to FB.

BR,

 

[drming]

Re: DCDC design issue

The feedforward component you mentioned is used for Lead(PD) compensator, so as to improve your phase margin. Please read p.p. 348

9.5.1 Lead(PD) compensator

Fundamentals of Power Electronics by R. W. Erickson ...

You can get the book at:

**broken link removed**

 

[tonywai]

DCDC design issue

thanks drming I have got the book!
thanks harrytrinh but I still want to know how to fulfill the internal compensation, BTW, in the datasheet i cannot find the Cff between FB and output.

 

[mycelldevice]

Re: DCDC design issue

Hi,

for voltage mode pwm control the compensation rc will always inside. because the cap is not big.

ths.

 

[shaq]

DCDC design issue

Dear all,

For current mode buck converter, how to design the error amplifier?

 

[tonywai]

DCDC design issue

Hi mycelldevice
for 10uh L 10uF C Fz is about 15KHz
compensation zero should be less than 15Khz
RC=10^-5
if R=500k C=20pF , and in type II and type III the zero should be 1/10 of Fz.
I don't think it can be integrated.

 

[dsPIC24F]

DCDC design issue

the tough part for SMPS is the noise generated by the power supply itself. I use metal shielding, still got some noise leaking. Tough to fight and it is case by case.

 

[babbage]

DCDC design issue

internal compensation is almost same as the external compensation. Loop stability issue

 

[peterwang]

Re: DCDC design issue

you have to watch latch-up issue for the power MOS due to the huge currents.

 

[liuyonggen_1]

Re: DCDC design issue

you have to watch latch-up issue for the power MOS due to the huge currents.

Could you tell me how to prevent latch-up issue?

Added after 31 minutes:

could someone explain the principle of softstart?

 

[sec]

Re: DCDC design issue

what is the difference between off-line converter and DC-DC converter ?

Added after 24 minutes:

a soft start circuit is when you want to pass from a DC level to a much higher level, if you do it instantaneously, the current in your switch (mos) will be to high and may burn it, a soft start adjust the duty cycle to start gradually.
Let say the impedance of the output circuit is just simple as a transformer, a diode a capacitor, and all other element of feedback are ideal. From 0 to 180 degree we have and RLC circuit. We assume that the switching frequency is 40KHz the impedance of the output circuit is given by

rootsquared(R^2+X^2)
where R is the resistance of the transformer
and X is |XL-XC|

let say the inductance of the transformer is 30uH ,the Capacitor is 100uF and the resistance around 0,1 Ohm, we then arrive to a value near 1.15 Ohm

So if you start (0V) to an output voltage of 12V it's 12 AMP !!

Please correct me is I'm wrong
I know I miss many things like the output of the transformer is pusle not AC like calculeted previously and