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Folded cascode is actually the OTA amplifier. So, there is only one dominant pole at the output node. The load capacitor itself behave as a compensation caps in the loop. Vary your capacitor until you achieved a sufficient phase margin.
I guess in your circuit, the bandwidth(UGF) is large, and load cap you set is small, you should decrease the input transistor's transconductance to, and
reduce the parasitic cap in your folded point to put the nondominant pole higher.
Something important, the number -45 might not be all that bad, it depends on your code. I once designed a circuit whose phase margin was 60, but the output from the simulator was -110 (I am not sure about the number though), check your code.
Yes: Folded cascode have dominat pole at the output because it is a voltage to current building block.
But: The intermediate stage in the folded cascode create a secondary pole, sometimes called parasitic pole. It is made by the diffusion diode caps found at the current summing node and the gate-source cap of the final current source, the cascode device and the transconductance of that device.
The trick: If the diffusion diodes are small in comparison to the gate-source cap of the cascode device you can make a technology match of the zero/pole compensation. Use a gate-oxide cap and a series resistance of a MOS equal to the cascode device. If you setup the equaltions for the second pole and the zero you will see the match. in practice you can cancel up to 20%. The second-pole/zero match is the factor which allows you to extend the phase margin in the presence of the process corners.
Enjoy the space of creativity, design and analysis.
I am interested in your points. Can you give me more details or materials about your trick ? As I know, the 2nd pole is around gm(cascode)/Cgs(cascode).
Usually, set the cascode devices smaller to get a good AC reponse.
what can be done is putting a capacitor between the folding node and the output node. This will basically by the miller multiplication effect seperate the first two poles of the folded cascode topology.
try and keep the w and l of the input MOS low.
this will reduce the cap at the folding node and this move further away from origin.
i tried this and obtained a PM of 90.
what can be done is putting a capacitor between the folding node and the output node. This will basically by the miller multiplication effect seperate the first two poles of the folded cascode topology.
Arsenic I am interested in knowing more about your method of compensation .Could you show me how or refer to a certain reference.........
thanks in advance
what can be done is putting a capacitor between the folding node and the output node. This will basically by the miller multiplication effect seperate the first two poles of the folded cascode topology.
hi arsenic I am interested in your method of compensation I even tried it it gave me a high PM but what I can't understand is that
when I varied the value of this capacitance from 0.25p to 1p the value of the bw decreased only about 20hz and the phase margin increased to 80degrees
so what is the explanation of this??
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