Comparison of Half Bridge Transformer Gate drive circuits

[cupoftea]

Hi,
Can you confirm that the IC based Half Bridge Gate Drive Transformer circuit attached is massively better than the BJT totem pole one? (LTspice sims and PDF schems attached)

The totem pole one suffers spurious turn on of a FET after the switching pulses are suddenly turned off due to eg output overload.

The totem pole one also lacks a hi side bias supply. This is essential here. If we examine the totem pole one, we can see that there are distinct intervals where the NFET is not actively held OFF by the PNP. (the PNP V(EB) is positive when the gate is low…meaning the FET is simply “kissed” OFF, and not properly “driven” OFF.)

…we all know what a “kissed ON” or “kissed OFF” FET is….its a FET which is driven on (or off), by application of a drive voltage…but then that drive voltage is removed, and the FET simply stays ON (or OFF) due to the charge stored (or not stored), in its Gate Source capacitance. In other words, a “kissed ON/OFF” FET is not properly held ON/OFF…and can be spuriously driven OFF/ON by some transient impacting through the FET junction capacitances.

In order to counter spurious oncoming of a FET after the switching pulses suddenly stop, severe damping is needed in the gate drive chain……..this damping means that a high side bias supply must be developed, otherwise the damping will deplete the gate drive current pulse. Hence the LT1693 IC based solution attached is better, would you agree?

 

[cupoftea]

The attached GDT for Half Bridge uses a single core for both secondaries. Also uses an UVLO for the hiSide IC.
It gives full drive (no "kissed FETs") for the FET due to the use of an IC, and not the dreadful "PNP turn off" thing.

Please evaluate and confirm, that having a hiSideBias is the only truly reliable way for use of GDTs?...the hiSideBias can either come from a separate SMPS, or from the gate drive transformer itself.

--- Updated Jan 2, 2022 ---

The attached is surely the best possible method to drive Half Bridge SMPS FETs...would you agree?
There is no way in the world that the FETs can be spuriously turned ON if the gate drive pulses suddenly vanish (as in eg overload shutdown). Also, the NCP5181 assures that no low voltage gate pulses are sent to the FETs due to NCP5181's UVLO of 8V.
The "Gate drive transformer" purely delivers the hi side bias for the NCP5181.....and due to the use of NCP5181...there is no "kissing" the FETs ON or OFF...so the FETs are solidly driven, and unlikely to be spuriously turned on by any kind of transient.
Would you agree?

--- Updated Jan 2, 2022 ---

hi

 

[FvM]

Your attempt to transmit two gate control signals plus driver power through a single transformer results in relative complex circuits and still some performance compromises.

I suppose that a straightforward solution with one power transformer and two opto isolated gate drivers performs better in terms of part count, occupied room, ruggedness, signal quality and even price. It should be included in the comparison.

 

[cupoftea]

I suppose that a straightforward solution with one power transformer and two opto isolated gate drivers performs better in terms of part count, occupied room, ruggedness, signal quality and even price. It should be included in the comparison.

Thanks,
I believe you mean as in the attached, but with an opto-isolated gate drive IC, instead of the NCP5181? {the NCP5181 (x2) is seen here driving the FETs}
(LTspice sim and PDF schem attached)