Compare Xilinx and Altera Datasheet?

[davyzhu]

Hello all,

I am reading the datasheet from Xilinx and Altera, they use the different name, e.g. CLB in Xilinx and CL in Altera, who know their equation, and how to compare?

Regards,

Davy Zhu

 

[Big Boy]

The CLB (CL) can make a lot of difference between the number of CLB used. I can't speak for @ltera as I havn't look into them, but the Xilinx use 4 logic cell per CLB (a logic cell sometime reffered to as a 'slice').

The best way to see them is in the datasheets, in the logic block description sections.

For example, in Xilinx, each of the four logic cells have 2 paths, with each path having it's own look-up table (LUT) and flip-flop. Plus, they have some extra logic gates, multiplexers and carry-chain to name only a few.

In each CLB, 2 of the 4 slices can be used as a more elaborate distributed RAM.

Also, keep in mind that CL/CLB are only a part of the chip. There are other very important parts that can be as important, mainly the IO blocks and block RAM, but also some other features like the clock managers.

 

[cawan]

Xilinx define FPGA consist of Common Logic Block (CLB). Each CLB consist of 2 (spartan, virtex) or 4 (virtex-2) slices. Each slice contain two LUTs and others logic unit such as MUX and XOR.

Altera define FPGA consist of Logic Block. Each Logic Block consist of Logic Element (LE) and LE contain LUT.

Notice that the both the LUT from xilinx and altera contain 4 fan-in and 1 fan-out. Stratix II from altera modified the basic architecture of LUT but still applied 4 fan-in and 1 fan-out architecture