red_0220
Junior Member level 1
Hi all
I plan to compare the difference between D-Flip-Flop and latch(Two Phase Clocking) performence in pipeline multiplier by Primetime tool.
But their minimun cycle time of clock are similar.
How can I prove latch(Two Phase Clocking) circuits is faster than D-Flip-Flop circuits by Primetime tool? Or only prove by waveform?
Measure the result as follows:
DFF pipeline:
Point Incr Path
--------------------------------------------------------------------------
.....
data arrival time 0.35
clock clk (rise edge) 0.50 0.50
clock network delay (ideal) 0.00 0.50
u1_mult4x4_U0_U2_U0_U0_C_r_reg_7_/CK (QDFFHTX1) 0.00 0.50 r
library setup time -0.14 0.36
data required time 0.36
--------------------------------------------------------------------------
data required time 0.36
data arrival time -0.35
--------------------------------------------------------------------------
slack (MET) 0.01
latch(Two Phase Clocking):
Point Incr Path
--------------------------------------------------------------------------
clock clk2 (rise edge) 0.25 0.25
.....
data arrival time 0.63
clock clk (rise edge) 0.50 0.50
clock network delay (ideal) 0.00 0.50
latout6_q_reg/G (QDLAHHTX1) 0.00 0.50 r
time borrowed from endpoint 0.13 0.63
data required time 0.63
--------------------------------------------------------------------------
data required time 0.63
data arrival time -0.63
--------------------------------------------------------------------------
slack (MET) 0.00
Time Borrowing Information
--------------------------------------------------------------
clk pulse width 0.25
library setup time -0.10
--------------------------------------------------------------
max time borrow 0.15
actual time borrow 0.13
--------------------------------------------------------------
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
.....
data arrival time 0.39
clock clk2 (rise edge) 0.25 0.25
clock network delay (ideal) 0.00 0.25
u1_mult4x4_U0_U1_latSS24_q_reg/G (QDLAHHTX1) 0.00 0.25 r
time borrowed from endpoint 0.12 0.37
data required time 0.37
--------------------------------------------------------------------------
data required time 0.37
data arrival time -0.39
--------------------------------------------------------------------------
slack (VIOLATED) -0.02
Time Borrowing Information
--------------------------------------------------------------
clk2 pulse width 0.25
library setup time -0.09
--------------------------------------------------------------
max time borrow 0.16
actual time borrow 0.12
THX~
I plan to compare the difference between D-Flip-Flop and latch(Two Phase Clocking) performence in pipeline multiplier by Primetime tool.
But their minimun cycle time of clock are similar.
How can I prove latch(Two Phase Clocking) circuits is faster than D-Flip-Flop circuits by Primetime tool? Or only prove by waveform?
Measure the result as follows:
DFF pipeline:
Point Incr Path
--------------------------------------------------------------------------
.....
data arrival time 0.35
clock clk (rise edge) 0.50 0.50
clock network delay (ideal) 0.00 0.50
u1_mult4x4_U0_U2_U0_U0_C_r_reg_7_/CK (QDFFHTX1) 0.00 0.50 r
library setup time -0.14 0.36
data required time 0.36
--------------------------------------------------------------------------
data required time 0.36
data arrival time -0.35
--------------------------------------------------------------------------
slack (MET) 0.01
latch(Two Phase Clocking):
Point Incr Path
--------------------------------------------------------------------------
clock clk2 (rise edge) 0.25 0.25
.....
data arrival time 0.63
clock clk (rise edge) 0.50 0.50
clock network delay (ideal) 0.00 0.50
latout6_q_reg/G (QDLAHHTX1) 0.00 0.50 r
time borrowed from endpoint 0.13 0.63
data required time 0.63
--------------------------------------------------------------------------
data required time 0.63
data arrival time -0.63
--------------------------------------------------------------------------
slack (MET) 0.00
Time Borrowing Information
--------------------------------------------------------------
clk pulse width 0.25
library setup time -0.10
--------------------------------------------------------------
max time borrow 0.15
actual time borrow 0.13
--------------------------------------------------------------
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
.....
data arrival time 0.39
clock clk2 (rise edge) 0.25 0.25
clock network delay (ideal) 0.00 0.25
u1_mult4x4_U0_U1_latSS24_q_reg/G (QDLAHHTX1) 0.00 0.25 r
time borrowed from endpoint 0.12 0.37
data required time 0.37
--------------------------------------------------------------------------
data required time 0.37
data arrival time -0.39
--------------------------------------------------------------------------
slack (VIOLATED) -0.02
Time Borrowing Information
--------------------------------------------------------------
clk2 pulse width 0.25
library setup time -0.09
--------------------------------------------------------------
max time borrow 0.16
actual time borrow 0.12
THX~