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Obviously,
FPGA Compiler is nothing when compared to amplify. I have worked with both of them a lot, for big designs. Amplify (which uses the same synthesis engine as Synplify) is much more powerfull. Synopsys has not done anything good in FPGA synthesis. Instead Amplify is almost a physical synthesizer. If you are doing big designs for one of Xilinx Virtex-II or Altera APEX-II FPGAs, and your design should work with high clock frequencies, (100MHz or more) FPGA Compiler will not do anything for you. Instead Amplify, I think is the best possible solution.
Even for small CPLD designs Synplify achieves better timing. If you have big FPGA designs forget about FPGA Compiler. I tried all synthesis tools available for FPGAs and Synplify (Amplify) is the best.
If in ASIC synthesis domain: De$ign Compiler ---> Phy$ical Compiler,
then in FPGA syhthesis domain: $ynplify ---> @mplify.
The major difference between Phys!cal Compiler/@mplifier and
Des!gn Compiler/$ynplifier is PC/@mplifier uses the physical information, i.e. it do, for example RTL-to-placed gate instead of DC/$ynplify do RTL-to-gate.
The benefit of doing logic synthesis with global placement is to get more accurate wire delay estimation! Because as the process scaling down, such as 0.25um, 0.18um, 0.15um or 0.13um, the propagation delay from the wire may be comparable to the gate delay :!:
Just a small remark; amplify supports only few FPGA devices from Xilinx and @lter@. So if you need CPLDs from those two companies already mentioned, and/or some FPGAs and CPLDs from other companies, you’ll need to use simplify.
Aalbu wrote: Even for small CPLD designs Synplify achieves better timing. If you have big FPGA designs forget about FPGA Compiler. I tried all synthesis tools available for FPGAs and Synplify (Amplify) is the best.
who can give a precise answer here..
how big the fpga design u encountered here?
My understanding is synplicity and fpga compiler are same old metamor clones...but gone through some minor transformations in the long run...Am i bashing on my own head here..i guess not!!!!!
But joe2moon made some meaningfull guesture here:..
Gate to wire delay needs bit more understanding, I reckon the standard optimization for such scales has lesser impact on synthesis tools, i mean in above sysnthesis tools user normaly has no option to pick and place such vendor protected chip internals.
One of my co-worker tested FPGA compilerII and synplicity. (Amplify I think is the physical optimization, it is still synplicity sythesis system.) FPGA compiler II compiles the code much faster than synplicity but the resulting FPGA runs a LOT slower and bigger. I also tried Xilinx XST. The compile time is a LOT slower than synplicity. So FPGA compiler II is the fastest compiler I ever tested and also the worst result (much worst, not even 50% of what synplicity gives in clock speed.) XST and synplicity were very close. In fact, if I remember correctly, XST results slightly high clock speed than synplicity but takes a little more gates. Also, XST has certain restriction on how I/O cell instantiate within hiarc level.
Overall, synplicity is the best tool. (It is even better if you bought amplify with it.) If you are using Xilinx and not willing to spend that much, XST is pretty good too, although the compile time is very slow on large design.
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