comparator

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end compare;

Code VHDL - [expand]
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end entity compare;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity compare is
port(    opcode: in std_logic_vector (8 downto 0);
destaddress:in std_logic_vector (4 downto 0);
clk: in std_logic;
fa_sign : in std_logic;
fb_sign: in std_logic;
fa_mantissa: in std_logic_vector (7 downto 0);
fb_mantissa: in std_logic_vector (7 downto 0);
fa_exp:in std_logic_vector (22 downto 0);
fb_exp:in std_logic_vector (22 downto 0);
alessb : out std_logic; 
aequalb : out std_logic; 
agreaterb : out std_logic;
unordered : out std_logic);
end entity compare;
 
architecture rtl of compare is
begin
process(clk,fa_sign,fb_sign,fa_exp,fb_exp,fa_mantissa,fb_mantissa)
begin
  if clk'event and clk='1' then 
    if opcode = "000000000" then
      if (fa_sign > fb_sign) then
        alessb<= '1'; 
        aequalb <= '0';
        agreaterb <= '0';
        unordered<= '0';
      elsif (fa_sign < fb_sign) then
        alessb<= '0'; 
        aequalb <= '0';
        agreaterb <= '1';
        unordered<= '0';
        if (fa_sign = fb_sign) then
          if (fa_exp> fb_exp) then
            alessb<= '0'; 
            aequalb <= '0';
            agreaterb <= '1';
            unordered<= '0';
          elsif (fa_exp< fb_exp) then
            alessb<= '1'; 
            aequalb <= '0';
            agreaterb <= '0';
            unordered<= '0';
            if (fa_exp= fb_exp) then
              if (fa_mantissa > fb_mantissa) then
                alessb<= '0'; 
                aequalb <= '0';
                agreaterb <= '1';
                unordered<= '0';
              elsif (fa_mantissa < fb_mantissa) then 
                alessb<= '1'; 
                aequalb <= '0';
                agreaterb <= '0';
                unordered<= '0';
-- lots of missing end if; statements if this is your intention.
    end if;
  end process;
end rtl;