comparator resolution in a ADC?

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patato

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comparator resolution

I know that for a N-bit flash ADC, it's comparator should have resolution higher than 1/2^N

but when it comes to a N bit pipeline ADC (1.5bit structure), does the same rule apply? or this requirement is somehow relaxed?
 

resolution of a comparator

no, it rlease the strickly of comparator resolution for it use redundancy digital code.
 

    patato

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1.5 bit adc, comperator

mists said:
no, it rlease the strickly of comparator resolution for it use redundancy digital code.
thanks for your reply!
one more question
i've read many papar said that in 1.5bit struture ADC, comparator "offset" can be tolerated up to 250mv(for 1V p-p input signal)

what's the difference between this "offset" and "resolution"?
 

difference between comparator and adc

Hi,
Offset and resolution are two different metrics for a comparator.

The resolution means the minimum voltage difference that the comparator can detect and give a logic (0 or 1) output. Offset is the errorband at input upto which the comparator cannot detect the above 'minimum voltage difference'. It is " 'offset' + 'resolution' " , which is, much importatnt from an ADC perspective.

For pipelined ADC implementation with 1.5bit perstage; the redundancy of 0.5bit perstage is used to relax the comparator performance requirement; esp. offset. You can go thru the following paper where this part is being discussed nicely.



hope would help u....
gd lk
sankudey
 

    patato

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flash adc comparator

note: offset has great effect on the resolution of comparator.
 

resolution comparators


tks a lot!
i've thought the "offset+ resolution" idea,but can't be sure.
Also, the paper is great. thanks!

Added after 4 minutes:

rficd said:
note: offset has great effect on the resolution of comparator.

i dont get it. I thought that offset and resolution are independent from each other?
 

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