thanks for your reply!
one more question
i've read many papar said that in 1.5bit struture ADC, comparator "offset" can be tolerated up to 250mv(for 1V p-p input signal)
what's the difference between this "offset" and "resolution"?
Hi,
Offset and resolution are two different metrics for a comparator.
The resolution means the minimum voltage difference that the comparator can detect and give a logic (0 or 1) output. Offset is the errorband at input upto which the comparator cannot detect the above 'minimum voltage difference'. It is " 'offset' + 'resolution' " , which is, much importatnt from an ADC perspective.
For pipelined ADC implementation with 1.5bit perstage; the redundancy of 0.5bit perstage is used to relax the comparator performance requirement; esp. offset. You can go thru the following paper where this part is being discussed nicely.
Hi,
Offset and resolution are two different metrics for a comparator.
The resolution means the minimum voltage difference that the comparator can detect and give a logic (0 or 1) output. Offset is the errorband at input upto which the comparator cannot detect the above 'minimum voltage difference'. It is " 'offset' + 'resolution' " , which is, much importatnt from an ADC perspective.