comparator for flash ADC of GPS front end receiver

[zzseason]

Hi,

I am currently working on flash ADC design for GPS front end receiver. I found many papers using latched type comparator but to reduce circuit complexity, I want to try to use opamp comparator in my design.

Can anyone guide me if I use the single stage opamp comparator in my design, what are the pros and cons? My design doesn't need very high sampling rate (>40MHz is enough).

Thanks in advance.

 

[dick_freebird]

Cons are, if you run it continuous-time your resolution is limited
by your natural distribution of Vio and your power is continuously
wasted. If you are pumping data out on a clock anyway, may as
well get the benefits of autozero and power strobing. There is
only one little slice of time you actually care about in a system
that samples synchronously.

I've built a flash front end for GPS and did it the way you
describe, just because it was easy and the bit count required
was low. But that doesn't make it the best solution.

 

[zzseason]

Thank you for explanation, Dick.
Do you have any reference paper on that design? Is it possible to share with me?

Thanks.