Comparator design in cadence

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kvk1806

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what is the initial region of operation for comparator when we use in 90nm in cadence?
 

That depends on your testbench setup (supply & stimuli)
and the circuit design (continuous-time, clocked, latched,
hysteretic or not, ...).

It has nothing much to do with tools or technology node.
 

i am using clocked comparaters and i want that the comparator should be operate in subthreshold i.e my supply vtg is 0.35v and while simulating i am not getting good freq i.e i am getting only in mega but i want that one should operate for high freq(ghz) so what are the options to increase freq for subthresold operation for better delay.
 

I think to achieve GHz frequency you will have to reduce the gm/Id value (i.e. --> moderate inversion mode), which means reducing the transistor W/L ratio or increasing the drain current. S. the following (general) GBW (fT) vs. gm/Id plot:
 

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