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Static timing analysis tools do setup and hold calculations based on 'early' and 'late' paths for clock and data.
For setup checks launch clock takes the 'late' path (max) and capture clock takes the 'early' path (min).
For hold checks launch clock is through the 'early' path and capture clock is the 'late' path.
For a synchronous design usually clocks for the launch and capture are coming from the same branch of a clock tree, so there's a common portion between these two paths which is originating from the same source.
So tools will calculate required and arrival times using late and early delays and finally adjust the delay calculation to cancel out the CPPR.
For setup checks :
Required time > Arrival time - CPPR
For hold checks :
Required time < Arrival time + CPPR
In both cases CPPR is going to reduce the pessimism in delay calculation.
The post above defines the problem pretty damn well. There are no alternative techniques to do CPPR as CPPR is a technique on its own. Just identify the gates shared by the launch & capture clock paths, reduce the 'spread' accordingly.