Common-mode Voltage of OPAMP

[ethan]

Hi there,

My question is that whether the input common-mode voltage has to be equal (or intend to set to be equal) to the output common-mode voltage of OPAMP for the general OPAMP design?

Thank you very much.

ethan

 

[yiyin]

Hi there,

My question is that whether the input common-mode voltage has to be equal (or intend to set to be equal) to the output common-mode voltage of OPAMP for the general OPAMP design?

Thank you very much.

ethan

you'd better use the same value for the input and output, if you want to make multi-stage system with one structure

 

[braudelk]

one of the benefits of fully differential opamp is that it can define common mode voltage for input and output independently.

 

[schwang1970]

yes you can use different cM voltage in fully differential opamp(ex:telescope op)

 

[Vamsi Mocherla]

Anyways, when you are closing the loop, the input and the output common mode voltages will remain the same in the case of a single ended amplifier. In the case of differential amplifier, you can play around with the output common mode level. But why do you want to do that?

 

[yiyin]

one of the benefits of fully differential opamp is that it can define common mode voltage for input and output independently.

wow, is it possible?
I am using a folded-cascode structure to design a continous-time ADC and have the same problem
I know op-amp with switched-capacitor can define the CM voltage independently
but what about continous-time?
Differnet CM voltages means different biasing conditions, which is really a problem in low voltage design....

 

[Vamsi Mocherla]

Well definately you can try for having a different common mode voltage levels irrespective of continous time or swit cap circuits. But it is not advisable to do it internally. A better way is to do a DC blocking at the output and then biasing the signal again to a different common mode voltage.