[SOLVED] Common mode gain is positive for extracted fully differential OTA

[monglebest]

I have the exact same problem as the below post, don't understand why the thread is closed and I still have no clue why I have positive common mode gain.
https://www.edaboard.com/showthread.php?384934-CMRR-is-less-than-the-DC-differential-gain

I use calibre, specifically select the ground node. All extracted sim results, noRC, CC,rcc_lm have positive common mode gain while prelayout has -42dB common mode gain. Simulated in open loop.
In transient open loop simulation, I am able to observe common mode transient gain, which confirms with me that the positive common mode gain is true. Prelayout and post layout have very closed match of differentail gain and BW after excluding input referred offset voltage.

 

[dick_freebird]

Re: common mode gain is positive for extracted fully differential OTA

First question is, does the layout pass LVS. Extracted, fine.
But is it the same in fact?

If you made the amplifier and its functions hierarchically
then you might be able to toggle the view (like Cadence
from a Hierarchy Editor session) and figure out what the
problem block was.

I don't see anything here about diligently probing key
nodes and branches in schematic and layout based runs,
across a pair of common mode input voltages (which
you might achieve by jacking the supplies instead)
and telling us all about what's moving and where it
differs, and where it all is on the schematic. That is
where I'd start, anyway.

 

[monglebest]

Re: common mode gain is positive for extracted fully differential OTA

First question is, does the layout pass LVS. Extracted, fine.
But is it the same in fact?

If you made the amplifier and its functions hierarchically
then you might be able to toggle the view (like Cadence
from a Hierarchy Editor session) and figure out what the
problem block was.

I don't see anything here about diligently probing key
nodes and branches in schematic and layout based runs,
across a pair of common mode input voltages (which
you might achieve by jacking the supplies instead)
and telling us all about what's moving and where it
differs, and where it all is on the schematic. That is
where I'd start, anyway.

Thanks for your reply, freebird.

The case is resolved. I talked with Junus2012, the owner of the previous post above. After carefully reviewing the open loop output with common mode input, I find the post-layout result is actually differential signal. Hence after obtaining the authentic Vcmout=(Voutp+Voutn)/2, the CMRR is aligned with prelayout.

It's interesting that AC analysis also reports the bogus CMRR.

So does PSRR.

 

[dick_freebird]

Try taking the differential output as the input terminals
of a vcvs and get a single ended ground referred output
that works better with classical test loops.