A
ahmadagha23
Guest

Hi
I have many constants in my VHDL code, which are used in some source code
files in my activhdl project. how can I define these common constant in a seprated file(pakage) in my project and use them in other files? Please describe the method for me.
Regards
I have many constants in my VHDL code, which are used in some source code
files in my activhdl project. how can I define these common constant in a seprated file(pakage) in my project and use them in other files? Please describe the method for me.
Regards