Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Common centroid arrangement in Capacitor Layout

Status
Not open for further replies.

ajay181

Newbie level 6
Joined
Feb 25, 2009
Messages
13
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Bangalore, India
Activity points
1,360
common centroid is share common top

Hi all,

a situation were i need to employ common centroid pattern for
capacitor layout.
Can the following be called a common centroid pattern..??
A A A A
B C D B
B E C B
A A A A
 

common centroid

Yes, it's quite ok. Don't forget the surrounding dummies, if you need high precision (now: C,D,E have all-side neighbors; A,B only partly). Dummies don't necessarily need to have the same dimensions (means: "thickness").
And you could still use the dummies as filter caps, e.g.
 

common centroid is better for matching capacitors

Thanks erikl,

yes, dummy cap cells will be put as a ring surrounding the active array.
But the confusing part is that we have lot many possible arrangemnts,.. like one below is another possibility..
A A B A
B C D A
A E C B
A B A A

so how to judge which one is the best option.. ??? what are the factors deciding .???
 

common centroid capacitor layout

This depends very much on the schematic connectivity of the array. If all caps share one common node - which is often the case - I'd suggest to make it the common bottom node. If you have an array of many single equal devices, of course it would be wise to have the same number of each in every row & column. This of course is not possible in your case. Here, a 2nd criterion comes up: Best possible distribution, which is your 2nd suggestion. However, the connectivity of the array also contributes to the asymmetry of the whole array. This asymmetry also must be held low enough, and this is probably easier with your 1st suggestion.
After layout you should check (simulate) the extracted netlist until its asymmetry (including connections to the rest of the circuit) is below your required value.
 
common centroid arrary

C, D and E are not common centroid but that is the best you can do in this diagram. Placing capacitors close together with surrounding dummies is often good enough. If these were bipolar transistors, common centroid would be much more important.
 

common-centroid capacitor layout

Thanks guys, for the valuable points
 

centroid arrangement matching

erikl said:
This depends very much on the schematic connectivity of the array. If all caps share one common node - which is often the case - I'd suggest to make it the common bottom node. If you have an array of many single equal devices, of course it would be wise to have the same number of each in every row & column. This of course is not possible in your case. Here, a 2nd criterion comes up: Best possible distribution, which is your 2nd suggestion. However, the connectivity of the array also contributes to the asymmetry of the whole array. This asymmetry also must be held low enough, and this is probably easier with your 1st suggestion.
After layout you should check (simulate) the extracted netlist until its asymmetry (including connections to the rest of the circuit) is below your required value.


hi i am back :)
erikl you said that it's advisable to use the common share node be made the bottom node. can you explain the reason ?
 

centroid arrangement of layout

ajay181 said:
erikl you said that it's advisable to use the common share node be made the bottom node. can you explain the reason ?
Wiring (routing) makes an important part of the parasitic capacitances, that's why it should be kept as simple as possible. Good routing matching ususally is much easier for the top plates, at least if you have a limited number of metal layers.
 

common centroid capacitor arrays

ok, now i am using Tr Cap ie. Gate 'plus' and S/D shorted for 'minus' . So it's better to use S/D for the common share node right ??
 

capasitor layout

ajay181 said:
ok, now i am using Tr Cap ie. Gate 'plus' and S/D shorted for 'minus' . So it's better to use S/D for the common share node right ??
Correct. Are you aware, that these Tr Caps (NMOS, if gate=plus) - because of the accumulation mechanism - are rather voltage-dependent? You can achieve a good matching only if they all have exactly the same voltage! If not, you can forget about matching!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top