combo logic /latch inference

[kil]

always @(posedge clk)
begin

a = b;
b = c;
c = a;

end

what logic it will get in the hardware. i think as it happening with respect to clk but list it may function as latch / some combo logic. i am confused can any one help in this regard.

regards
kil

Added after 10 minutes:


hi,

it may not infer as latch as latch will be infered if else part is missing in the if else statment with respect to clock. it will infer as combo logic but but what the actual hardware implementation of it is what i excaly looking for...

Thanks
KIL

 

[research_vlsi]

It will infer Flip Flop..

Synthesis ur example and check.

 

[basha_vlsi]

hi
it will infer flops only but that is bad coding style.

use non blocking statements and u can change order of those assignments

if u want to use blocking then u have to aware of sequence of the assignments to be write

 

[amittewarii]

It will infer 3 flops ..

 

[shweta_eda]

hey it will infer ffs.........since code is sensitive to clk......use nonblocking staements to avoid this case........

 

[raulyrx]

always @(posedge clk)
begin
a = b;
b = c;
c = a;
end
It will infer 3 ffs ..
if coding like this
always @(posedge clk)
begin
c = a;
b = c;
a = b;
end
It will infer 1 ffs ..
but use nonblocking staements
always @(posedge clk)
begin
c <= a;
b <= c;
a <= b;
end
It will infer 3 ffs ..

 

[gaobin0628]

three flip-flops cascade

 

[cihchenlin]

raulyrx
is right