Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Combinational logic for frequency division

Status
Not open for further replies.

blanket

Junior Member level 3
Joined
Jan 14, 2003
Messages
28
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
310
It came up in a general banter session to check if it's possible to divide frequency of a digital waveform by only using combinational logic (of course with no output fed back to inputs)? It's quite easy to create a frequency multiplier. But is a frequency divider possible?

Thanks,
b
 

coshkun

Full Member level 2
Joined
Aug 27, 2005
Messages
126
Helped
18
Reputation
36
Reaction score
10
Trophy points
1,298
Activity points
2,214
If you connect 2 JK flip-flops in series you can divide frequency in two ,3 JK flip flop you can divide 4 ...

All the Js and Ks are connected to logic 1
Signal--->CLK1 Q1--->CLK2 Q2----->CLK3 ....
Q1=f/2
Q2=f/4
 

blanket

Junior Member level 3
Joined
Jan 14, 2003
Messages
28
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
310
With due respect, please read the topic patiently while you plan to post a solution. The point is use of only combinational logic for frequency division. A flip flop is an inherent sequential circuit. So that isn't the solution. In fact it's a T flip flop that we should use where J and K are tied high. The question is usage of combinational gates without feedback.
 

Resistance

Member level 4
Joined
Dec 24, 2005
Messages
74
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,288
Activity points
2,034
hi friend,

actually i guess we can realize ff using muxes right ? would that not be enough..

If not do tell abt the comb freq multiplier and divider both.. its interesting ..
 

blanket

Junior Member level 3
Joined
Jan 14, 2003
Messages
28
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
310
So let me level set before we try finding a solution.

You can actually construct a frequency multiplier by passing a signal through an XOR gate while the other input is tied to the delayed version of the first input. For example you can tie input A to the signal and input B to the signal that passes, lets say, 10 invertors. Now this, because of the propagation delay, will generate pulses where the two inputs were out of phase with each other. And since this occurs twice every cycle, we have an output thats twice the frequency of the input signal.

The question now is on a similar setup or a complex one is it possible to come up with a frequency divider. Your multiplexor example is still not good, because you will tie the output to one of the inputs of the multiplexor thus a feedback from output to the input exists.

More bluntly put, is it required to "remember any previous value" for a circuit that you would construe to divide the frequency?

I hope I made it clear. It may happen that we do not have a circuit at all. But if we have that'd be a great debate on it!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top