#### vijay82

##### Member level 2

An FSM, M, is constructed by connecting the output of a 3-state FSM to the inputs of an 9-state FSM. M is then reimplemented using a state register with the minimum number of bits. What is the maximum number of bits that may be needed to reimplement M?

It would seem the number of states in the new reimplemented FSM would be 12 but is 27, as given in the answer at the same place.

Isn't it logical to think the same 3+9 states would be coded in the new FSM, with transitions in the last 9 states depending on the output from the first 3 states (looking at it from an RTL coding perspective). Can anyone give an explanation for states being multiplicative (3*9) than additive(3+9)?