Combination Loop in Verilog

[Chan Lu]

So I wrote this for a Radix-4 Booth multiplier, and it worked for a functional simulation in Modelsim, but not so much for a timing simulation. When compiled in Quartus II it gives me a few combinational loop warnings, 'Warning: Found combinational loop of <2> nodes'. I'm not quite sure what's wrong or how to fix these, any ideas?

`timescale 1 ps/ 1 ps
module booth (Clock, Resetn,Start,Mplier,Mcand,Done,Product);
parameter n = 8;

input [0:0] Clock,Resetn,Start;
input [n-1:0] Mplier;
input [n-1:0] Mcand;

output wire [0:0] Done;
output wire [n+n-1:0] Product;

reg [0:0] don;
reg [n+n-1:0] prod;
reg [0:0] newDone;
reg [n+n-1:0] Prodnext;
reg [n:0] A,B, Anext, Bnext;
reg [1:0] state, nextstate;
wire [n:0] C;
integer count, newCount;


assign Done = don;
assign Product = prod;


localparam state1 = 2'b01, state2 = 2'b10, state3 = 2'b11; 

assign C = {Mcand[n-1],Mcand[n-1:0]};

initial
begin
  nextstate = state1;
  count = 0;
  don = 1'b0;
end

always@(posedge Clock or negedge Resetn)
begin
  if(~Resetn)
    state = state1;


  state = nextstate;
  A = Anext;
  B = Bnext;
  count = newCount;
  don = newDone;
  prod = Prodnext;

end

always @(*)
begin


  case(state)

    state1: 
    begin
      if(Start)
      begin
        newCount = 0;
        newDone = 1'b0;
        Anext = 0;
        Bnext = {Mplier,1'b0};
        nextstate = state2;
        Prodnext = {A[n-1:0],B[n:1]};
      end       
       
      else
      begin
       newCount = count-1;
       if(count == 0)
         newDone = 1'b0;
       else
         newDone = Done;
       Anext = A;
       Bnext = B;
       nextstate = state1;
       Prodnext = {A[n-1:0],B[n:1]};
      end

    end

    state2:
    begin
      case(B[2:0])
      3'b001: Anext = A + C;
      3'b010: Anext = A + C;
      3'b011: Anext = A + (2*C);
      3'b100: Anext = A - (2*C);
      3'b101: Anext = A - C;
      3'b110: Anext = A - C;
      default: Anext = A;
      endcase 

      nextstate = state3;
      Bnext = B;
      newDone = Done;
      newCount = count + 1;
      Prodnext = {A[n-1:0],B[n:1]};

    end

    state3:
    begin
      Bnext = {{A[1],A[0]},B[n:2]};
      Anext = {{A[n],A[n]},A[n:2]};
      newCount = count;
      Prodnext = {A[n-1:0],B[n:1]};
      if(count > (n/2-1))
      begin
        nextstate = state1;
        newDone = 1'b1;
      end
      else
      begin
        nextstate = state2;
        newDone = 1'b0;
      end

    end

  endcase   

end

endmodule

 

[FvM]

If you don't immediately see the problem, you'll first read the warning details. Which nodes are involved in combinational loops? This allows at least to focus your debugging work.

I guess, the problem is only brought up by a wrong structure of the edge sensitive always block. It's missing an "else begin end" clause.