Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Coding style for flip flops

Status
Not open for further replies.

vaisram

Member level 1
Joined
Dec 2, 2010
Messages
32
Helped
6
Reputation
12
Reaction score
5
Trophy points
1,288
Activity points
1,469
I read in a book that all inferred flip-flops of a given function or even groups of functions should be described using a single procedural block/process. And multiple procedural blocks/processes should be used to model larger partitioned blocks within a given module/architecture.

Why is this so?
 

This sounds like something from ESA's guidelines. This is done to improve simulation time. The intention is to minimize the number of signals in the design, preferring variables instead. This is done as a simulation optimization. by using one process, only connections to other modules will need to be signals.
 
Hi permute.. i think u got my question wrong.. i dint ask why we use variables instead of signals.. the question is:
Why do we group related signals in the same process statement? What will happen if we assign unrelated signals in the same process statement???
 

Oh, that would be for readability.

if you use a separate process for each signal, the code becomes cluttered and it becomes hard to determine which signals are conceptually related to other signals. On the other side, if you assign unrelated signals within a process, it makes these signals appear conceptually related to the rest of the signals in the process. In more extreme cases, like when only one process is used in a file, it can make it hard to determine which signals are conceptually related.

Some people take this idea a bit further, and use blocks, or comments, to denote groups of related logic -- processes, assignments, components, ect...
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top