coding for T flip flop - error on q_s is not systhesisale on

[mohan_ece]

coding for T flip flop

here i write code for t flip flop
While synthesising it shows error on q_s is not systhesisale one..
i dont know wat to do to correct it.
i hope someone clarify it ..
need it soon plz.



entity tflipflop is
Port ( t : in STD_LOGIC;
reset,clk : in STD_LOGIC;
q : out STD_LOGIC);
end tflipflop;

architecture Behavioral of tflipflop is
signal q_s:std_logic;
begin
process(clk,reset,t)
begin
if(reset='1')then
q_s<='0';
if(clk'event and clk='1')then
if(t='1')then
q_s<= not q_s;
end if;
end if;
end if;
q<=q_s;
end process;
end Behavioral;

 

[Maxwell077]

Re: coding for T flip flop

True version of your code
Do not forget the library declarations...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity tflipflop is
Port ( t : in STD_LOGIC;
reset,clk : in STD_LOGIC;
q : out STD_LOGIC);
end tflipflop;

architecture Behavioral of tflipflop is
signal q_s:std_logic;
begin

process(clk,reset,t)
begin
if(reset='1')then
q_s<='0';
elsif(clk'event and clk='1')then
if(t='1')then
q_s<= not q_s;
end if;
end if;
q<=q_s;
end process;
end Behavioral;