ammassk
Member level 2
Dear all
I wrote a Vhdl code for checkinh the number id positive or negative. In simulation I am getting the answer. But the code is not synthesizable. I used the format as shown below.
if(clk='1' and clk'event)then
if(ready0='1')then
if(y0(y0'left)='1') then
alpha0<="1111111111111111";
end if;
end if;
end if;
Please help me to make it synthesizable.
I wrote a Vhdl code for checkinh the number id positive or negative. In simulation I am getting the answer. But the code is not synthesizable. I used the format as shown below.
if(clk='1' and clk'event)then
if(ready0='1')then
if(y0(y0'left)='1') then
alpha0<="1111111111111111";
end if;
end if;
end if;
Please help me to make it synthesizable.