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code is not synthesizable

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ammassk

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Dear all

I wrote a Vhdl code for checkinh the number id positive or negative. In simulation I am getting the answer. But the code is not synthesizable. I used the format as shown below.

if(clk='1' and clk'event)then
if(ready0='1')then
if(y0(y0'left)='1') then
alpha0<="1111111111111111";
end if;
end if;
end if;
Please help me to make it synthesizable.
 

TrickyDicky

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there is nothing wrong with the code you posted as it is, but without context we cant tell what the problem is. Im guessing there are problems elsewhere in the code. Please post the whole code.
 

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