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Code for scanning 4x4 hex keypad in verilog- Not working

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pranavm1502

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This code was implemented on a CPLD but it is not working. Please help!
// This code should show the position of the push-button pressed by glowing appropriate leds.

Code Verilog - [expand]
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module hex(col,row,led);
output reg [3:0]row,led;
input [3:0] col;
integer r,c,val;
always@(col )
begin
    //row=1;
    led=0;
    r=3;
    //while (col);
    while(r>=0)
    begin
        row=4'b0000;
        row[r]=1;
        for(c=0; c<4;c=c+1)
        begin
            val=col[c];
            if(val==1)
            begin   
                led= 4*(r) +c+1;
                
            end     
        end
        r=r-1;
    end
end             
endmodule

 
Last edited by a moderator:

vhdl and verilog are not programming languages. They describe hardware circuits.

You are trying to write a program. Your verilog tries to scan keys step by step. Have you just adapted this from a microcontroller keypad scanning routine you found on the internet?

You need to rethink it all, I'm afraid. Try drawing a circuit that can scan a keypad and produce a single code. Decide if it will only accept a single key down at once or multiple. Decide how you will debounce the keys.
 
Last edited:
I have adapted it from keypad datasheet. This is written just to see if I can interface it. While checking I am pressing only single key till i get stable output, so debouncing and whether to accept single or multiple can be worked out later.

I have tried to make always@() work on clock pulse instead of on col(column). But the same problem is perpetuating i.e. it works properly only for r=0 (first row). I also found that only first row is high and other rows are low all the time.

Code:
module hex(col,row,led,clk);
output reg [3:0]row,led;
input [3:0] col;
input clk;
integer r,c,val;
always@(posedge clk )
begin
	led=0;
	r=3;
	while(r>=0)
	begin
		row=4'b0000;
		row[r]=1;
		c=0;
		while(c<4)
		begin
			val=col[c];
			if(val==1)
			begin
				led= 4*(r) +c+1;
				c=c+1;
			end
			else
			c=c+1;
		end
		r=r-1;
	end
end				
endmodule
Is there fault in logic?
 

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