code for cross clock domain DATA

[FixitFast]

Helloo every one


I need to ask about the following code if it works fine in the practical two cross clock domain systems.
in simulation it works but I have reservations since this method looks fine for 1-bit signals, but for a data bus I am not sure hence want to ask

module clk_2_cross ( clock1, clock2, rst_n, data_in, data_out);

 

input clock1;

input clock2;

input rst_n;

output [7:0] data_out;

input  [7:0] data_in;

reg [7:0] data_out_meta; 

reg [7:0] data_out_reg; 

reg [7:0] data_out_reg_r;

wire[7:0] data_out;

 

// Assign statements

assign data_out = data_out_reg_r;

 

// Always block to declare  synchronous logic from source clock domain 

always @ (posedge clock1) 

begin

  data_out_meta <= data_in; 

end

// Always block to declare synchronous logic in destination clock domain

 

always @ (posedge clock2 or negedge rst_n) 

begin

  if (! rst_n)

  begin

     data_out_reg <= 'b0;

     data_out_reg_r <= 'b0;

  end

else

begin

  data_out_reg <= data_out_meta;

  data_out_reg_r <= data_out_reg;

 end

end

endmodule

Thank you

 

[TrickyDicky]

this will work safely (ie. you wont have any meta stability) but you could get incorrect data, depending on the clock relationships. Double registering is much safer for single bits, and slow => fast transition. It is much safer to use a FIFO for data busses.

 

[ads-ee]

This won't work in a real device. Each bit is being demetted separately, which will result in unreliable transfers. You need to either use a FIFO or if the data that is crossing the clock domains only changes after being stable for many clock cycles (e.g. an enabled output register, resynchronize the enable in the other clock domain)

Note: Using a FIFO will be much easier.

Regards