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Co-simulation of Analog & Digital cells

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moisiad

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Hi all

I am doing analog design in cadence enviroment using Spectre. Can you please inform me how can i simulate analog cells (in transistor levels) along with digital cells (in verilog). I assume that the difficulty is to translate the logical levels of the digital cells in analog signals recognisable from the analog part.

Thanks
 

To simulate chips in transistor level, you can try Synopsys' Powermill or Nanosim
 

we can use the simulators VCS or verilog AMS for mixed signal simulations.
 

anjali said:
we can use the simulators VCS or verilog AMS for mixed signal simulations.


Hi

Have you a sample tutorial or code of mixed signal with synopsys VCS?
The complexity is no matter.


tnx
 

some examples might be given in VCS user guides. please refer..
i too didnt use vcs much.
 

You can use the SpectreVerilog option to simulate your circuit.I think that can help you.You should create a .config file in your circuit view first.
 

you can use vcs+manosim to simulate
vcerilog+Spectre to simulate the mixed-signal simulation
 

For digital and analog cosimulation several AMS tools are available from various vendors like cadence,mentor,synopsys.
 

HSIM can do it very elegently, as long as you can convert verilog/vhdl to spice netlist. The rest are just like spice simulator.
 

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