Cmos static power dissipation

[Manuv16589]

In 'Cmos digital integrated circuit by sung mo kang' there is a line that states "static power dissipation is very small and is essentially limited by leakage current of pmos transistors". How does pmos helps to reduce static power? Thanks in advance

 

[thunderdantheman]

PMOS doesn't help to reduce power... in fact it's less efficient that NMOS but we need both in logic. I think what that line means is, if it wasn't for the short falls of PMOS then static power consumption would be nearer to zero. (Someone might want to confirm if NMOS have similar leakage figures as PMOS - I'm not sure, but both would leak some small amount).

Just to detail it, static means sitting there doing nothing... May as well turn it off! CMOS devices use both NMOS and PMOS switching devices both of which have capacitive gates... to turn one on you need a current pulse to charge up the gate capacitance and activate the switch. So you've just used a minuscule amount of power to charge up the gate... to turn it off, you shunt the gate capacitance to ground... and there you have it, power consumed. Put a few million of these minuscule MOS devices in a chip and clock them at a few 100MHz and fewwwww.... get yourself a decent power supply!