CMOS RFIC corner simulation

[wccheng]

cmos corner simulation

Dear all,

Now, I design the RFIC circuit using CMOS technology. For the commerical consideration, it is necessary to simulate the cirucit in corner state (such as ss, tt and ff). Because of this, I have several questions:

(1) I find that I need to use larger current source in the ss state in order to make my RF circuit (such as vco) is still working. However, it may violate my orignal design specification. How could I fix it? Sometimes, vco could not work at ss model state even I tune it.

(2) If I need to make my circuit also workable in ss, tt and ff state, it might use different current source. How could I implement it? For example, I have one LNA. It may need to consume 15mA, 10mA and 7mA for workable at ss, tt and ff state respectively. How could I make 3 different current source in the one LNA?

Thanks

wccheng

 

[milkdragon]

vco corner simulation

I think you can add some switches (Digital) for different current bias, this should be pretty straightforward.

 

[jecyhale]

corner simulation

I have two suggestions,
First is use the PTAT as the current reference.
Second is use SPI to control