CMOS logic gates and digital circuits in 0.18u process

[bmwin]

minimum size inverter for 0.18u cmos process

Hello,

In my design there is the Digital control part, so I want to ask about digital design in CMOS 0.18u process. I'm now using Cadence 5141. How about the W and L when we design logic gates such as: inverter, NAND2, NAND3, NOR, XNOR,... and other parts?
Is there any standard for these?
Can you tell me some experience when we design digital part in CMOS process?
Thank you very much and goodbye.

BMWIN.

 

[evilguy]

0.18u std cell area

usually in digital logic, designer always use the standard cell provides by the foundry. usually foundry has stated in their pdk the type of logic gates whether the gates have been optimized for speed, low power or area. If you need to do custom design, minimum size is good to achieve better speed. but as i know using standard cell is much easier and faster rather than custom design.

-evilguy-

 

[forkschgrad]

cmos logic gates

that's true. It's quite complicated to design digital logic because of the complexity of construction. It needs a careful circuit simulation and analysis.

 

[bmwin]

cmos logic

I'm using General PDK, but unfortunately it's don't have digital standard cells.
I hope that everyone will give me some other advices. Thanks alot.

 

[hr_rezaee]

0.18u layouts

Hi
use emule.
regards

 

[raduga_in]

0.18u digital cmos process

Please refer to the attached document .. it gives you the methdology
to choose a perticular W and Ls for the gates for particular loading
conditions. This methodology is known as method of "Logical effort"
nicely given is the Ivan Sutherland's book and a bit in Jan Rabey's book.

 

[raduga_in]

rabeys book of cmos

Btw, In digital design we have to keep the length minimum possible
in order to use the full speed of the technology..

 

[floatice]

logic gate design using 0.18u technology

The W and L of logic circuit is the function of Speed and the load.You can get them by carefully simulation.

 

[bmwin]

to raduga_in: I have read your document and have found some books such as: CMOS Logic circuit design [John P.Uyemura, Springer]... It's really complicated to design multi stage digital circuit in CMOS process.
I'm just starting with analog design and I don't have so much time for this project. So, I'll try to find Process Design Kit for 0.18u process that includes the logic standard cells.

to hr_rezaee: can you tell me the name of the PDK above??

I hope to receive your advices soon. Thank you very much.

 

[evilguy]

i'm just a bit confuse. you want to design analog or digital circuit? or mixed signal circuit?

if you design mixed signal, what i can suggest is, the digital part, you design using VHDl or verilog. simulate it. then using appropriate tool you can easily convert your design to layout using standard cell that you mention it. i never do this before since i custom made my layout but i heard it is possible to do that.

 

[bmwin]

Thank u, evilguy.
I want to design mixed signal. An 8-bits integrating (dual-slope) A/D converter. In this design, there are analog parts (integrator, comparator, bandgap voltage reference) and digital parts (counter, latch, register, switch,...)
I'll try your way 'cause it's really difficult to use custom digital part way in this project. Do you agree?

Added after 10 minutes:

On the same occassion, can anybody give me some documents relate to 8-bits integrating (dual-slope) AD converts design?? especially the digital control part and in the 0.18u process

Thanks very much.

Regards.

 

[evilguy]

I'll try your way 'cause it's really difficult to use custom digital part way in this project. Do you agree?

yes, it is impractical if you custom made digital part because digital part consist of a lot of transistors. i custom made my layout because up till now my circuit is pure analog. good luck.

 

[Teddy]

How about to log to ARM.com and get it through them?

 

[adpot]

i am trying to design a Register which works at 6 Ghz... i tried various sizing for the transistors...but the maximum it works is 1 Ghz.....i am using 0.18um CMOS technology.....i know the minimum sizing that can be used in 0.18 technology is 270nm... can u help me out..

 

[husseinadel]

when you intend to design a controls for a certain block ; most probably analog or rf , you can use standard cell library for the given tech. so that you can optimize by yourself in layout or it doesn`t worth doing rtl for it , you can search for artisian ; a company that do std cells for different tech.

 

[ravitest]

follow the following book

digital design by hodges, i am not sure about title but author is correct.

 

[adpot]

what do u mean by optimizing in layout?? i am not doing a layout.. i am designing only the schematic...the 32 bit register ..to be precise serial input parallel output register .. is only a part of my complete design...