cmos leakage and average current

[Sambhav_1]

How does the average current and leakage current depends when the devices get fast as compared to previous process?

 

[dick_freebird]

Faster means shorter L which generally means
more leakage but this has many "moving parts".

Faster also can be had with lower VT and this is
common in modern nodes, a plurality of VT
shots allowing users to pick speed or leakage
as their main concern, device by device.

If you go low VT and short channel it's likely
that your leakage will be FET subthreshold
conduction (with a steaming glob of DIBL
on top) and decades above the junction
leakage floor.

Average current is a combination of DC
leakage (Nnmos*Inmos+Npmos*Ipmos
divided by some fudge factor for what
logic state exposes what devices to full
voltage) and AC displacement current in
the gate capacitances (incl G-D Miller)
and routing capacitances and the
cross-conduction interval. As you increase
speed, you increase drive (Ishoot-through)
but decrease the time it persists. Low VT is
worse than high VT for this. Smaller devices
have smaller capacitances. Interconnect
however behaves more as a "line
capacitance" than a "plate capacitance in
modern nodes, linewidth being lower than
ILD thickness at least in the lower levels.