Cmos inverter glitch

[kingearlkwan]

HI ALL,

I have recently designed a simple inverter using cmos and simulate it in tspice using level1 characteristics. Problem is that I'm seeing glitches during transition from logic o to 1 and vice versa. Does anyone know how to remove this glitch and what causes this glitch?

Thanks.

 

[keith1200rs]

You haven't shown a schematic or results but my guess would be feedthrough due to gate-drain capacitance. Add a small load to the output.

Keith