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CMOS Class C VCO - pre & post layout simulation discrepa

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post layout simulation

I'm designing a vco at 8GHz. I'm seeing discrepancies between the pre & the post layout simulations especially with regards to the tail current which has jumped to twice as much. The output power is also down by 4dB. Any idea what to see in order to fix this problem?
 

pre layout simulation

Look at the STI parameters (sa sb sc) before and after extraction for the current mirrors.
 

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