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CMOS chips are less stress resistant than bipolar or BICMOS chips?

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treez

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Hello,
The UCC28C45 chip is "bicmos". Why did they not just make it completely CMOS?....Is it because CMOS is more delicate than bicmos?, and indeed, pure bipolar technology is the most robust of all, but is less efficient?

ucc28c45 datasheet
https://www.ti.com/lit/ds/symlink/ucc28c45.pdf
 

HTA

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Hi Treez,

the 18V input voltage is the driving requirement for BiCMOS. Modern CMOS processes have a 7V or less voltage capability. Also for industrial 24V interfaces BiCMOS is a common interface technology for microcontroller(https://www.ichaus.de/wp1_mcu_interface ).

Enjoy your design work!
 
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and bipolar is always more rpobust to ESD type damage than CMOS?....just as signal FETs are more damage prone than signal BJTs.?
 

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BJTs lack the fragile thin oxide of the gate. You can still
do hot carrier type damage with an ESD event, and drift
your front end out of offset spec or Iio/Iib, but you're not
likely to see the functionality compromised.

The reason for BiCMOS in that Unitrode part is, the op amp
and reference especially are easier to design and work better
(and would likely be reused from predecessor all-BJT parts)
than a 40V CMOS (just look at VT match and VT drift on that
kind of fat old MOSFET) but your logic and your output and
its taper chain are so much better off as saturation-free
MOS logic. You can make a NMOS-over-NPN, PMOS-over-PNP
output stage with nice switching characteristics (clamp B to C,
most bias current comes from load, Vcb>=0). With an all-BJT
scheme you have to throw a lot of bias current to cover the
low temp corner and then pay the switching speed price at
the hot corner.

Designing ESD protection for 40V analog inputs is a real joy,
and -needing- to do it (CMOS) is not as nice as getting away
with not putting it on ("everybody's used to 500V ratings, it's
a linear").
 
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