CMOS 3 stage Ring Oscillator, the design-steps

[mixedsignal]

Hi,

I want to design a 3-stage ring oscillator with each stage as a common-source amplifier having resistive-load. Is it possible to realize with common-source amp with resistive load? If yes, please let me know the design-steps. Before connecting the stages how I should bias each stage? If possible please suggest me a reference.

I have attached the schematic I want to try out.

Thanks & Regards
Sam

 

[dick_freebird]

CMOS Ring Oscillator

It is possible. However, so few stages and high bandwidth
may give you startup and/or amplitude problems. Getting to
a "saturated" output amplitude requires enough phase shift
and gain-at-frequency to make full swing.

More stages will be slower, but more robust.

The common-source, resistor-loaded style ought to be fairly
self-biasing.

 

[dameash]

@dick_freebird : I am trying to simulate a 3 stage common source amplifier to make a ring oscillator. I have given Vdd and ran the simulation for transient analysis. I do not see any oscillation. I am seeing only the dc voltage at the output of each stage. Can you tell me where i am going wrong.

- - - Updated - - -

@dick_freebird : I am trying to simulate a 3 stage common source amplifier to make a ring oscillator. I have given Vdd and ran the simulation for transient analysis. I do not see any oscillation. I am seeing only the dc voltage at the output of each stage. Can you tell me where i am going wrong.

 

[micpro]

try changing the R value and W/L? If you make R too small and W/L too small, then a MOS won't pull enough current to bring down the gate of the next one.

 

[mdeepak12]

I do not see any oscillation. I am seeing only the dc voltage at the output of each stage. Can you tell me where i am going wrong.

since you are running transient analysis and if all your components are ideal, the circuit might not oscillate. There are two options for this.

1) Run PSS and it should run fine

2) In transient analysis force one of the cap to be charged at the start which creates a non ideality. This can be done by making "init" of any one of the cap to be 1 V.

Regards,
Deepak