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CML Ring VCO (Fvco decreases with Higher Itail?)

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celebrevida

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I'm researching CML Ring VCO design. I found this paper:


The basic design is this:
1600893896598.png


Instead of a fixed tail current, you can made it programmable like so.
1600894160927.png
1600894309332.png


But their Fvco vs Itail result is baffling me.
I though Fvco would increase with higher Itail. The result in their paper shows the opposite.

That am I missing???

Thanks for any insight.
 

If higher tail current takes you further out from threshold
but does not result in proportionate slew rate enhancement,
it will take you longer to slew back across threshold on the
return.

It might be interesting to look at what happens at the lower
ITAIL end, whether there is a region of monotomically rising
fOsc there and your graph is maybe taken from an "over
the top" bias range.
 

If higher tail current takes you further out from threshold
but does not result in proportionate slew rate enhancement,
it will take you longer to slew back across threshold on the
return.

It might be interesting to look at what happens at the lower
ITAIL end, whether there is a region of monotomically rising
fOsc there and your graph is maybe taken from an "over
the top" bias range.

What does that mean "tail current takes you further out from threshold"?
What threshold are you talking about?
 

The threshold for logic state. Which probably also
moves as you jack the tail current.

The more you overtravel past threshold, the more
distance to come back the other way hence more
delay.

Why don't you plot yourself families of switching
waveforms and see what's happening?

Also it appears that the load FETs ought to have
their current scaled similarly to the tail but you
show no such thing. Maybe this is the problem,
upping the tail current might "bury" the diff pair
drain like I'm talking about.
 

The threshold for logic state. Which probably also
moves as you jack the tail current.

The more you overtravel past threshold, the more
distance to come back the other way hence more
delay.

Why don't you plot yourself families of switching
waveforms and see what's happening?

Also it appears that the load FETs ought to have
their current scaled similarly to the tail but you
show no such thing. Maybe this is the problem,
upping the tail current might "bury" the diff pair
drain like I'm talking about.

Okay I've had time to put together a version of this circuit using LTSpice.

If you fix the vctrl (the PMOS active load gate voltage), Fvco increases with Itail initially. I believe in this region the PMOS active loads are in triode.

But then I think the PMOS active loads start going into saturation region. At this point increasing tail current actually causes Fvco to go down. I am thinking that it is because the Rds of the PMOS is starting to become higher with more tail current. And thus RC time constant is getting high and is a bigger factor than higher tail current.

Finally if tail current is high enough, I see that Fvco stops decreasing and even slightly increases. I guess at this point PMOS is well in saturation and Rds of those devices is no longer changing much and more tail current again results in increasing Fvco.

The paper I looked up only showed Fvco decreasing with fixed vctrl and increasing tail current. So I guess it must be operating in that region where PMOS loads are around the knee of the IV curve and transitioning from triode to sat region.

But it seems to me a better design is to use current mirroring and adjust vgs of the tail current and PMOS active loads together as you say. The designer of the paper chose not to do that for some reason and adjust the vgs of the PMOS active loads and the tail current independently.
 

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