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[SOLVED] CML divider by 2 clarification

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khalifas

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I am trying to design a CML divide-by-2. consisting of 2 cml latches (master and slave). I need to know what dc level i need for the the clk as i found that a small shift in that level could make the circuit doesn't divide properly.
Also one more thing what happens when both latches are on (clk and clkb are around the common mode value).
I am working on 0.13u technology and a biasing current of 300u and load of 2k.
latch circuit is attached.

Thanks in advance.
 

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