Clocks in SDC and corresponding creation of similar clocks at no particular pin

[sun_ray]

Why do we put some virtual clocks in SDC along with the actual clock. For example if I create a clock named system_clk with 400 MHZ fequency at a pin named sys_clk, we also create a virtual clock named virtual_system_clk and we do not create this virtual clock at any pin as we create the system_clk at sys_clk. What are the necessity of those virtual clocks?

 

[nisshith]

virtual clocks are clocks which are essentially to models the clocks outside chip. They are used while analysis of Input-> reg or reg->output paths.

 

[sun_ray]

virtual clocks are clocks which are essentially to models the clocks outside chip. They are used while analysis of Input-> reg or reg->output paths.

Nisshith

We could do the modelling of the Input-> reg or reg->output paths with the main clock instead of the virtual clock. What are the reasons that we separately declare a virtual clock for modelling Input-> reg or reg->output paths? Can you please let me know?

To explain the matter with the above example of system_clk, we could do the modelling of Input-> reg or reg->output paths by the system_clk itself rather than the virtual_system_clk. In that case we need not to create an extra clock named virtual_system_clk. What are the advantages for creating an extra clock named virtual_system_clk?

Regards

 

[nisshith]

Firstly, It may happen that the Virtual clock (Clocks capturing or launching data to IO ports) does not have same frequency as the system clock.
Also the points launching or capturing these data are not actually on the chip therefore we cannot define the end points in clock tree.

 

[sun_ray]

Firstly, It may happen that the Virtual clock (Clocks capturing or launching data to IO ports) does not have same frequency as the system clock.
Also the points launching or capturing these data are not actually on the chip therefore we cannot define the end points in clock tree.

nisshith

Can you please provide some drawbacks for defining this type of virtual clocks? Probably there will be some drawbacks for issues with OnR for these virtual clocks. Can you please provide also some more advantages and reasons for creation of this virtual clocks?

Thanks for your reply.
Regards

 

[nisshith]

there are no drawbacks in defining virtual clocks its a requirement you have to do it. If you don't your path remains unconstrained and you would not be able to analyze I/O paths. whenever there is a path between a flip flop sitting outside the chip and a flip flop sitting inside the pin, we need a clock for the flip flop sitting outside the flip flop since our system clock cannot act as a CLK for that flip flop therefore we define a virtual clock for that flip flop. The flip flop sitting outside may be a capture or the launching flip flop and that data is launched / captured on the edge of this virtual CLK