Clocks from same source, need any constraints ?

[imbichie]

Hi All,

I am using Xilinx Virtex7 FPGA for my design and tool using is xilinx Vivado.
In my design there are signals which are driven by CLKA domain and going to CLKB domain and vice verse.
But CLKB is twice the freq as CLKA and both are coming from same source PLL.
So whether I should give any constraints in this case?

 

[ads-ee]

Unless otherwise specified, as being asynchronous, all clocks are considered synchronous in Vivado. So timing will be considered between CLKA and CLKB domains.

Regards

 

[imbichie]

Hi ads-ee,

Thank you for your reply.

I have grouped the CLKA and CLKB in the same group when I give asynchronous group constraints ("set_clock_group -asynchronous -group {CLKA CLKB} -group {CLKC}").
So my doubt is whether I am missing any other constraints between CLKA and CLKB domains.

 

[ads-ee]

Shouldn't be any other constraints required between CLKA and CLKB if you specified the PLL input clock constraint correctly. Vivado should create generated clocks for the output of the PLL. My advice check the timing reports for unconstrained paths.