Clocks for generating the DQS strobe signal in DDR RTL

[avantika10]

Hi all,
I've a doubt in generating the DQS strobe signal in DDR RTL. It should be generated for both positive and negative edge of the clock.

My question is, from the implementation point of view, do we use a generated clock which is negative of global clock(or a phase difference of 180) to do this ? or do we get two incoming clocks, clka and clkb from the dll for this? which one is better ?

Thanks.

 

[kib]

Re: clocks in DDR core

There are 2 ways to clock a DDR flop's
Below image shows the same
I have normally used the inverter inside the IOB to invert the clock and has worked for me without any problem. I have target tested my design upto clock speed of 166MHz.

Regards
kib[/img]

 

[rjainv]

clocks in DDR core

Or you can do a final launch on clk running at twice freq, and do SDR->DDR conversion before that.

 

[atuo]

Re: clocks in DDR core

Hi all,
I've a doubt in generating the DQS strobe signal in DDR RTL. It should be generated for both positive and negative edge of the clock.

My question is, from the implementation point of view, do we use a generated clock which is negative of global clock(or a phase difference of 180) to do this ? or do we get two incoming clocks, clka and clkb from the dll for this? which one is better ?

Thanks.

Hi,

If you use FPGA to implement, you can get DCM to generate a phase difference of 180. But for ASIC, I think use the posedge and negedge to latch data.

Thanks.

Thaks.

 

[avantika10]

clocks in DDR core

Hi,
i'm not implementing in fpga. it has to be in asic. thats the problem.

if its in fpga, i can use a 2x clock from DCM and try to use that instead of the global clock. so, i don't have to look for both edges. since its in asic, i'm looking at alternate methods of implementation of RTL.

 

[rjainv]

clocks in DDR core

a DLL will be costlier. You need DLL only if each edge matters ( like incoming dqs), and there is a difference in waveform if you invert it or do a 180degree phase shift.

If you have a free running clock, I believe you can straight go for negedge of clock.
But if you are designing inbound stage, working on dqs sent by DRAM to you, you need to be careful. You can use negedge there too, but you don't have a lot of them. There is precisely one edge per data bit, so if you have to re-capture on strobe, then you ought to use DLL or add a lot of buffer delays to create zero-cycle paths.