clocking the Virtex II Pro Eval board.

[suddy72]

Thanks to everyone who helped me with my last problem with this board.

I now would like to ask a question about the clocking on the board. What i am hoping to do is connect up an ADC to this board so that it can process the digital output. The ADC board itself outputs a clockout. I would like to use this clock out as the main clock for the FPGA instead of the system clock that they already provide. I am just wondering does anyone know how i configure the board so that this is the case ?

Stuart

 

[JPR75]

Xilinx's FPGA have several CLK inputs.
Usually, in the Eval board, one is connected to a local oscillator and others are accessible for the user.
Have you checked the schematics of your Eval board for other GCLK ?
Choosing what GCLK is used inside the FPGA is done with the constraint editor.

 

[suddy72]

sorry i am new to all this, what is GCLK ? Global Clock ? and you say that to set up which clock you are using as the main clock , you do it in the UCF file ?

 

[JPR75]

Global Clock ?

Yes

you do it in the UCF file ?

Yes

 

[suddy72]

Thanks for all your help.

I now need to try figuire out just which pin on the FPGA i attach my signal to.