Clocked process triggered by pulse signal (VHDL question)

What I would like to do is to execute a clocked process whenever the rising edge of a pulse arrives. Here is my code:

I heard that there should be only one clock for one process, but my code seemed to have two clocks. Is my above code OK to work in hardware? If no, is there any other method to achieve what I need? Thanks guys.

You code won't work in hardware, there are no dual clock registers in any existing FPGA.

1. If pulse is synchronous with respect to clk, then use pulse as an enable.

2. If pulse is asynchronous wrt clk and pulse has a width that is less than the clock period, then you'll have to pulse stretch pulse. You could use a second process to do this using an async set or reset connected to pulse. Most FPGAs have limited access to clock input pins of the registers from the logic fabric, so it's better to avoid using rising_edge(pulse) to detect an edge. Note: the output of this needs to be synchronized using clk

3. If pulse is async but wider than a clock period (plus set/hold margins) than, synchronize it using two flip flops and perform a synchronous edge detection (a third FF and a gate to look at the 3rd and 2nd FF outputs for 3rd=0 and 2nd=1, i.e. the leading rising edge)