clock with varying phase in verilog

[vivek]

verilog phase shift

hi
i have a clock in my design, from which i should get another clock with varying phase diference with the original one. how can i do this in verilog. code need not be synthesisable since this is for a model. the resulting clock should have different phase difference at each cycle compared with the original clock.
thanks in advance

 

[eeeraghu]

verilog phase delay

As you are saying that it need not be synthesizable u can add intra or inter assignment delays with few combinational logic and sequential logic (a flip flop feedbacking it with xor and the original clock

 

[JesseKing]

how to generate phase shifted clock in verilog

for phase shift, you will need a high frequency clk to generate your original clk and phase-shift clk.

 

[nand_gates]

clock shifting in verilog

Here it is what ur looking for!
Hope this helps!

module clk_delay(/*AUTOARG*/
   // Outputs
   clk_out, 
   // Inputs
   clk, delay
   );
   input clk;
   input [31:0] delay;
   output      clk_out;
   reg         clk_out;
   
   always @(clk)
      clk_out <= #(delay) clk;
   
endmodule // clk_delay

module test();
   reg                  clk;                    
   reg [31:0]           delay;               
   wire                 clk_out;              
   clk_delay clk_delay(/*AUTOINST*/
                       // Outputs
                       .clk_out         (clk_out),
                       // Inputs
                       .clk             (clk),
                       .delay           (delay[31:0]));   
   initial begin
      $shm_open("WAVEFORM");
      $shm_probe(test, "AS");
      
      clk = 0;
      delay = 0;
      #1000  delay = 0;
      #1000  delay = 1;
      #1000  delay = 2;
      #1000  delay = 3;
      #1000  delay = 4;
      #1000  delay = 5;
      #1000  delay = 6;
      #1000  $finish;
   end
   always #5 clk = ~clk;
   
endmodule // test

 

[vivek]

phase shift clock generator + verilog

hi nand gates
that method works. i also tried another way. i generated another clock(higher freq) and muxed the two clocks. the results were good

 

[Jenjel]

Re: phase shift clock generator + verilog

hi nand gates
that method works. i also tried another way. i generated another clock(higher freq) and muxed the two clocks. the results were good

ok, so if we want to generate a clock with parameters like phase, duty high, duty low and which synthetisable, what can we do ?
Any suggestion plz ?
Thank you !