clock uncertenty vs freq increase

[ivlsi]

Hi All,

Might increasing the Clock Frequency replace Clock Uncertainty definitions?

I understand that increasing the clock frequency doesn't issue new hold violations. But on another hand, the hold violations should not be solved during the logic synthesis (just during layout phase). So, why should we still deal with clock uncertainty?

Thank you

 

[morris_mano]

the interconnect delay during synthesis is just wire load model which may have some margin error on delay calculation compare to actual interconnect delay after Place&Route. To account for this difference, some uncertainty margin is added during synthesis for hold .

 

[slutarius]

Hi All,

Might increasing the Clock Frequency replace Clock Uncertainty definitions?

I understand that increasing the clock frequency doesn't issue new hold violations. But on another hand, the hold violations should not be solved during the logic synthesis (just during layout phase). So, why should we still deal with clock uncertainty?

Thank you

You can make that because it is all the same effect at Synthesis step.
Later on, you need to add them back in order to see all kinds of factors. It is necessary for STA analysis.