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Clock uncertainty in Synthesis and static timing analysis.

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vid31

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Hi,

I have started working on STA and Synthesis.

Can anyone help me how to predict values of clock uncertainty,clock transition,input transition,input/output delay,etc.?


I know that it depends on design as well as clock frequency but is there any relation between these values and clock period like clock uncertainity is 4% of clock period?
 

zjushmily

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Every company has their own deisgn flow and design margin according their libarary.

So. If you want to do synthesis or pre-layout STA, you must follow that margin guider, for example, ZWLM, 55% clock cycle as shrink ratio.
And for input/output delay, you can make it tighten enough in order to make STA result better.
 
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soloktanjung

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Hi,

I'm also searching for that. I read in one tutorial in the internet that they use charaterize command in DC or refer to the datasheet for set_input/output_delay value.

Hairo
 
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vid31

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Thanks,

Hairo, would you provide me that tutorial....

Thanks,
Vid31
 
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rca

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The clock uncertainty should also contain the jitter, if the clock generator is made by a collegue, just ask him the specification.
The duty cycle could also impact if you use both edges flip-flop design, from rise to fall and fall to rise, that "overconstraint" the clock max frequency if the duty cylce is 45%/55%.
 

vid31

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@ rca,

but what value should be provided to overconstraint for 50% duty cycle clock?
Is there any convention in that?

Thanks,
vid31
 

pavanks

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Normally for i/o delays they do budgetting. Like say 70-30 if u dont get these from the top level designer.

Uncertainty would not be more than half cycle of ur clock. so max 50% of ur clock.

Clock transition u can set diff values and check how is ur insertion delay and skew. This value must be within the min and the max transition values.
 

soloktanjung

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Hi Vid31,

This is the tutorial I mentioned. Hope it helps you.

Best,
Hairo
 

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  • Synthesis-flow.pdf
    3.1 MB · Views: 115

vid31

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Hi,

Does anyone know how to generate list of registers those are clocked by perticular clock?

I want the list of registers per clock domain.

Is there any command in design compiler?

Regards,
Vid31
 

oratie

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Hello,

all_registers -clock <clock_name>
 
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vid31

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Hi oratie,

Thanks...
Thank you very much..

Regards,
vid31
 

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