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Clock tree synthesis skew groups and clock trees

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devaVLSI

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Hi...i am trying to understand what is the relation between skew groups and the clocks ...suppose a sew groups has 10 sinks and all the sinks are getting A, B and C clocks and a single sink point has different latency for clock A, B and C then how to find what is causing the other sinks to delay more and . Is it due to skew group or clocks ?
 

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